Engineering · AI · Chip design
During my 24 years at Synopsys, I worked as both an R&D manager and an engineer on the front end of Design Compiler and Fusion Compiler. I’m a former co-chair of the IEEE 1800 SystemVerilog Basic Committee.
I’ve initiated architectural changes, guided engineering teams, and resolved difficult language and synthesis problems for major chip-design customers. I enjoy connecting the technical details to the larger decision: what needs to change, why it matters, and how to make it work in an industrial system.
I’ve been using AI directly in software modernization and refactoring. I’m also examining how AI changes engineering practice, the economics of design exploration and evaluation, and the architecture needed for intelligent systems to act reliably over time.
Current work
How the actions of consequential agents change the conditions for their future competence
An engineering framework for systems whose actions change both the world and their own ability to act competently later.
Upstream Search, Downstream Truth, and the Migration of Scarcity in Chip Design
How cheaper AI-driven exploration shifts scarcity toward trusted evaluation, engineering memory, authority, and technical capital.
A Research Program for Temporary, Governed, and Revocable Intelligence
A research program for placing capability temporarily under explicit resource, authority, reserve, and exit commitments.